Design of In-Memory Parallel-Prefix Adders

Computational methods in memory array are being researched many emerging technologies to conquer the ‘von Neumann bottleneck’. Resistive RAM (ReRAM) is a non-volatile memory, which supports Boolean logic operation, and adders can be implemented as sequence of operations memory. While in-memory have recently been proposed, their latency exorbitant for increasing bit-width (O(n)). Decades research computer arithmetic proven parallel-prefix technique fastest addition conventional CMOS-based binary adders. This work endeavors move significantly minimize addition. Majority was chosen fundamental primitive synthesized majority were mapped using proposed algorithm. The algorithm used map any adder mapping performed such way that minimized. enables O(log(n)) array.